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GENLINX TMII GS9023
Embedded Audio CODEC
PRELIMINARY DATA SHEET FEATURES * single chip embedded audio solution * operates as an embedded audio multiplexer or demultiplexer * full support for 48kHz synchronous 20/24 bit audio * 4 channels of audio per GS9023 * cascadable architecture supports additional audio channels * multiplexes and demultiplexes arbitrary ANC data packets * support for 143, 177, 270, 360 and 540 Mb/s video standards * full processing of audio parity, channel status and user data * multiplexes and demultiplexes audio control packets * EDH generation and insertion when in Multiplex Mode * 3.3V core with 3.3V or 5V I/O (requires 5V supply) * complies with SMPTE 272M A, B, and C APPLICATIONS SDI Embedded Audio ORDERING INFORMATION
PART NUMBER GS9023-CFY PACKAGE 100 pin LQFP TEMPERATURE 0C to 70C
DESCRIPTION The GS9023 is a highly integrated, single chip solution for the multiplexing/demultiplexing of digital audio channels into and out of digital video signals. The GS9023 supports the multiplexing/demultiplexing of 20 or 24 bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be sample rate converted to 48kHz before and after the GS9023 using audio sample rate converters. Each GS9023 supports all the processing required to handle the multiplexing/demultiplexing of four digital audio channels. To simplify system design, the GS9023 seamlessly integrates with common AES/EBU digital audio receivers and transmitters. The cascadable architecture allows for the multiplexing/demultiplexing of additional audio channels with no external glue logic. The GS9023 supports video standards with rates from 143Mb/s to 540Mb/s. When in Multiplex Mode, the GS9023 supports the generation and insertion of EDH information according to SMPTE RP165. In combination with Gennum's GS9032, the GS9023 provides a low power, highly integrated two chip solution for SDI transmit applications. In combination with Gennum's GS7005, the GS9023 provides a low power, highly integrated two chip solution for SDI receive applications. The GS9023 requires a 3.3V power supply for internal core logic and a 3.3V or 5V power supply for device I/O.
GS9023
WCINA/B AINA/B AUXEN
2 3 Convert Input Data Format Convert AES/EBU Format
MPX
S/P 10
MPX MPX 10 10 10 Audio Buffer 10 MPX
AM[2:0] SAFA/B CSA/B UDA/B VFLA/B MUTE ADDR[3:0] CS, WE, RE DATA[7:0] DIN[9:0] VM[2:0]
3 Convert Control Code
8
Add CRC 10 MPX Generate Audio Packets 8 Arbitrary Packet Buffer
Add EDH
10 DOUT[9:0]
7 8 10 3 Control Registers
9 b9=b8
10
Video Detection & Synchronization
Generate ANCI area 9 LOCK PKT[8:0] EDH_INS
MULTIPLEX MODE BLOCK DIAGRAM
Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 45 - 05
TRS 10
ANCI DIN[9:0] 10 Video Detection & Synchronization
Delete ANCI 10
Delete TRS
DOUT[9:0]
GS9023
Detect ANCI 10 Output Arbitrary Packet Output Control Code
3
LOCK BUFERR AUXEN PKT[8:0] SAFA/B CSA/B UDA/B VFLA/B WCOUT
9
8
Audio Buffer Control Registers
10
P/S
Add CRC
Convert Output Data Format Convert AES/EBU Format 3 AM[2:0]
2
AOUTA/B
7
8
ADDR[3:0], CS, WE, RE
DATA[7:0]
MUTE
DEMULTIPLEX MODE BLOCK DIAGRAM
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PIN CONNECTIONS
TEST DATA2 DATA1 DATA0 GND BUFERR NC LOCK VDDIO DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 GND DOUT8 DOUT9 AOUTA AOUTB WC OUT NC VDDIO
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 GS9023 38 88 37 89 (TOP VIEW) 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDDIO DATA3 DATA4 DATA5 DATA6 DATA7 GND RE WE CS ADDR3 ADDR2 ADDR1 ADDR0 VDDINT ANCI TRS EDH_INS MUTE AM2 AM1 AM0 GND ACLK GND
GND PKTEN PKT0 PKT1 PKT2 PKT3 PKT4 PKT5 PKT6 PKT7 PKT8 VDDIO AUXEN CSB CSA UDB UDA VFLB VFLA SAFB SAFA GND TEST TEST VDDINT
GS9023
VDDINT VM2 VM1 VM0 DEMUX/MUX DIN9 DIN8 DIN7 DIN6 DIN5 GND DIN4 DIN3 DIN2 DIN1 DIN0 VDDINT
NOTE: The GS9023 DOUT[9:0] MSB to LSB convention is compatible with the GS9022 but reversed with the GS9032 or GS7005. See Interconnection with GS9032 or GS7005 section.
PIN DESCRIPTIONS
NUMBER 1, 17, 26, 90 2-4 SYMBOL VDDINT VM[2:0] I TYPE DESCRIPTION +3.3V power supply pins for core logic. Video standard format. Used in conjunction with the TRS pin. VM[2] is the MSB and VM[0] is the LSB. See Table 1. Mode of operation. When set HIGH, the GS9023 operates in Demultiplex Mode. When set LOW, the GS9023 operates in Multiplex Mode. Parallel digital video signal input. DIN[9] is the MSB and DIN[0] is the LSB. The digital video input should contain TRS information. Device ground.
5
DEMUX/MUX
I
6-10,12-16
DIN[9:0]
I
11, 23, 25, 29, 50, 58, 71, 82, 98, 100 18 19
GND
RESET WCINA
I I
Device reset. Active low. 48kHz word clock for channels 1 and 2. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode. 48kHz word clock for channels 3 and 4. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode.
20
WCINB
I
3
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RESET WC INA WC INB AINA AINB GND PCLK GND
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PIN DESCRIPTIONS (Continued)
NUMBER 21 SYMBOL AINA TYPE I DESCRIPTION Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Video clock signal input. Connect to ground. Start of audio frame indicator for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. SAFA is HIGH for audio frame 0 and LOW for all other audio frames. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Start of audio frame indicator for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. SAFB is set to HIGH for audio frame 0 and LOW for all other audio frames. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Validity flag for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. VFLA is HIGH when audio is invalid and LOW when audio is valid. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Validity flag for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. VFLB is HIGH when audio is invalid and LOW when audio is valid. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. User data for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. User data for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Channel status for channels 1 and 2. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Channel status for channels 3 and 4. Valid only for non-AES/EBU audio formats. This pin should be grounded when inputting AES/EBU audio data. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. Extended audio enable. When HIGH, the GS9023 processes 24-bit audio samples. When LOW, the GS9023 processes 20-bit samples. In Multiplex Mode, this pin is an input and is supplied by the user. In Demultiplex Mode, this pin is an output and is generated by the GS9023. +3.3V or +5V power supply pins for device I/Os. In order for device I/O to be +5V tolerant VDDIO must be +5V. Device I/O are not +5V tolerant if VDDIO is +3.3V.
22
AINB
I
GS9023
24 27, 28, 75 30
PCLK TEST SAFA
I I/O
31
SAFB
I/O
32
VFLA
I/O
33
VFLB
I/O
34
UDA
I/O
35
UDB
I/O
36
CSA
I/O
37
CSB
I/O
38
AUXEN
I/O
39, 51, 67, 76
VDDIO
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PIN DESCRIPTIONS (Continued)
NUMBER 40-48 SYMBOL PKT[8:0] TYPE I/O DESCRIPTION Arbitrary data I/O bus. In Multiplex Mode, the user must input the arbitrary data packet words starting from the secondary data identification (SDID) to the last user data word (UDW) according to SMPTE 291M. The GS9023 internally converts the data to 10 bits by generating the inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023 outputs the arbitrary data packet words starting from the SDID to the last UDW. PKT[8] is the MSB and PKT[0] is the LSB. See Figures 9 and 13. Arbitrary data packet enable. In Multiplex Mode, PKTEN must be set HIGH one PCLK cycle before Arbitrary packet data is input to the device. In Demultiplex Mode, the output is set HIGH when outputting Arbitrary packet data. See Figures 9 and 13. No Connect. Do not connect these pins. 48kHz word clock for channels 1, 2, 3 and 4. Valid only when operating in Demultiplex Mode. Audio signal output for channels 3 and 4. The AES/EBU digital audio output is biphase mark encoded. In all non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 1 and 2. The AES/EBU digital audio output is biphase mark encoded. In all non-AES/EBU modes, the output is not bi-phase mark encoded. Parallel digital video signal output. DOUT[9] is the MSB and DOUT[0] is the LSB. Lock indicator. In Multiplex Mode, when HIGH, the video standard has been identified, the start of a new video frame has been detected and the device is multiplexing audio. NOTE: LOCK will not be set HIGH unless at least one of the audio channel enable bits is HIGH. See "CHACT" description in Table 14. In Demultiplex Mode, when HIGH, the video standard has been identified, the `lock' process selected by "ACTSEL" has been validated and the device is demultiplexing audio. See "ACTSEL" description in Table 15. NOTE: LOCK remains active regardless of the number of audio samples in the video stream after `lock' is achieved. 70 BUFERR O Buffer error. Indicates when an internal buffer overflow/underflow error has occurred. Valid only when the device is configured to operate in Demultiplex Mode. NOTE: If an internal buffer overflow/underflow condition occurs, the GS9023 does not mute the audio output. 72-74, 77-81 83 84 85 86-89 91 DATA[7:0] RE WE CS ADDR[3:0] ANCI I/O I I I I I Host Interface data bus. DATA[7] is the MSB and DATA[0] is the LSB. Read enable for Host Interface. Active LOW. Write enable for Host Interface. Active LOW. Chip select for Host Interface. Active LOW. Host Interface address bus. ADDR[3] is the MSB and ADDR[0] is the LSB. ANCI Selection. Valid in Demultiplex Mode only. When set HIGH, each ancillary data packet with a DID corresponding to either the audio packet DID, the extended audio packet DID or the arbitrary packet DID is removed from the video signal. The data contained in the packets are output at the corresponding pins. The various DIDs are user programmable in the internal registers and are accessible via the Host Interface. NOTE: When ancillary data packets are deleted, the GS9023 does not recalculate the EDH checkwords. When set LOW, all ancillary data packets remain in the video signal.
GS9023
49
PKTEN
I/O
52, 69 53
NC WCOUT
N/A O
54
AOUTB
O
55
AOUTA
O
56, 57, 59-66 68
DOUT[9:0] LOCK
O O
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PIN DESCRIPTIONS (Continued)
NUMBER 92 SYMBOL TRS TYPE I DESCRIPTION TRS Selection. Used in conjunction with the VM[2:0] pins to select video standard format. In Multiplex Mode, when the TRS pin is HIGH, TRS is added to a composite video signal. In Demultiplex Mode, when HIGH, TRS is removed from a composite video signal. See Table 1. EDH Insert Selection. Valid in Multiplex Mode only. When set HIGH, the GS9023 performs EDH functions according to SMPTE RP165. When set LOW, EDH is not inserted. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in the internal registers via the Host Interface. 94 MUTE I Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are forced to `0'. In Demultiplex Mode, when set HIGH, the output data is forced to "0". Audio mode format. In Multiplex Mode, AM[2:0] indicates the input audio data format. In Demultiplex Mode, AM[2:0] indicates the output audio data format. AM[2] is the MSB and AM[0] is the LSB. See Table 2. Input audio signal clock (128 fs). Synchronous to PCLK.
93
EDH_INS
I
GS9023
95-97
AM[2:0]
I
99
ACLK
I
NOTE: All unused inputs of the GS9023 should be connected to ground.
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DETAILED DESCRIPTION The GS9023 has two main modes of operation: Multiplex Mode and Demultiplex Mode. In Multiplex Mode, which is selected by setting the DEMUX/MUX input pin LOW, digital audio is embedded into a digital video stream. In Demultiplex Mode, which is selected by setting the DEMUX/ MUX input pin HIGH, digital audio is extracted from a digital video stream. Tables 14 and 15 contain Host Interface Register descriptions for the Multiplex and Demultiplex Modes respectively.
MULTIPLEX MODE Video Clock Input
When "VSEL" is LOW, the video input standard is selected by the VM[2:0] and TRS input pins. When "VSEL" is HIGH, the video input standard is selected by the "VMOD[2:0]" and "D2_TRS" bits in Host Interface Register #0h. The supported video input standards are listed in Table 1. After the user has specified the video input standard via the VM[2:0] and TRS pins or by setting Host Interface Register #0h, the GS9023 performs video standard detection to verify that the input video stream corresponds to the selected standard. When the selected video input standard is verified, the "VXST" bit of Host Interface Register #0h is set HIGH. The LOCK output pin and the "LOCK" bit of Host Interface Register #0h are then set HIGH if at least one of the audio channel enable bits "CHACT(4-1)" of Host Interface Register #1h is HIGH and the start of a video frame is detected. NOTE: The user must ensure that the video input format correctly corresponds to the video format being provided to the GS9023.
GS9023
A master video clock must be supplied to the PCLK pin corresponding to the selected video standard. The supported video input standards and corresponding clock frequencies are listed in Table 1.
Video Data Input
The video data DIN[9:0] is clocked into the GS9023 on the rising edge of PCLK. The video clock frequency must correspond to the video input standard selected. This is done via the "VSEL" bit of Host Interface Register #0h.
TABLE 1: Video Input Formats SERIAL DIGITAL DATA RATE (Mbps) 143 143 270 360 540 177 177 270 360 540 540 PCLK FREQUENCY (MHz) 14.3 14.3 27.0 36.0 54.0 17.7 17.7 27.0 36.0 54.0 54.0
VIDEO STANDARD
VM[2] or "VMOD[2]" 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VM[1] or "VMOD[1]" 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VM[0] or "VMOD[0]" 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TRS or "D2_TRS" 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
525/D2 (SMPTE259M) 525/D2 (SMPTE244M) 525/D1 Reserved 525/16:9 Reserved 525/4:4:4:4 (System #1) Reserved 625/D2 (with TRS) 625/D2 (without TRS) 625/D1 Reserved 625/16:9 Reserved 625/4:4:4:4 (System #2) 625/4:2:2P (System #4)
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Video Data Output
The video signal is output at the DOUT[9:0] pins. The video signal is synchronized to the rising edge of PCLK. When the GS9023 is properly configured, audio packets, extended audio packets, audio control packets and arbitrary data packets are multiplexed into the output video signal. When the video signal is a 525 line or 625 line D2 format, TRS information is added to the video signal if the TRS input pin or the "D2_TRS" and "VSEL" bits of Host Interface Register #0h are HIGH. EDH packets can also be inserted into the video signal by setting the EDH_INS pin HIGH or by setting the "EDHON" bit HIGH of Host Interface Register #1h. When selected, the GS9023 inserts EDH packets according to SMPTE RP165. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in Host Interface Registers #Eh and #Fh. NOTE: In the 525/4:4:4:4 video standard, EDH packets should not be inserted as this can lead to TRS signal corruption. When EDH packets are not inserted, the "EDHDEL" bit of Host Interface Register #0h controls the deletion of EDH packets. When the "EDHDEL" bit is set LOW, EDH packets are deleted from the incoming video signal. When "EDHDEL" is set HIGH, EDH packets pass through the device unchanged. NOTE: "EDHDEL" functionality is valid only when the "CASCADE" bit of Host Interface Register #4h is LOW.
Audio Clock Input
The GS9023 supports muting of the audio data input. Multiplexed audio and extended data packets for all channels are forced to zero when the MUTE pin or "MUTE" bit of Host Interface Register #4h is set HIGH.
Control Code Input
When inputting non-AES/EBU audio data, the validity (V), user data (U) and channel status (C) bits of each audio data channel must be input to the corresponding pins (VFLA, VFLB; UDA, UDB; CSA, CSB). The signals must be updated on the rising edge of WCINA/B and remain constant for the entire word clock period (64 ACLK cycles). When inputting non-AES/EBU audio data, the SAFA and SAFB pins must be high for one frame out of 192 frames received to indicate the start of frame condition. When inputting AES/EBU audio data, the control code input pins should be grounded as they are not used.
TABLE 2: Audio Input Formats FORMATS AIN-MODE 0 WCINA/B User Supplied User Supplied User Supplied User Supplied Not Used AM[2] 0 AM[1] 0 AM[0] 0
GS9023
AIN-MODE 1
0
0
1
AIN-MODE 2
0
1
0
AIN-MODE 3
0
1
1
A master audio clock (128 fs: 6.144MHz) must be supplied to the ACLK pin. This clock must be synchronized with the video signal input to the GS9023. An audio word clock must also be supplied (fs: 48kHz) to the WCINA/B pins when using non-AES/EBU audio. The two 48kHz word clocks must also be synchronized to the video signal.
Audio Data Input
AIN-AES/EBU Not Used Not Used Not Used
1 1 1 1
0 0 1 1
0 1 0 1
The serial audio data for channels 1 and 2 are input to the AINA pin. The serial audio data for channels 3 and 4 are input to the AINB pin. The GS9023 can multiplex 20 or 24 bit audio data samples. When the AUXEN pin or bit "A4ON" of Host Interface Register #1h is HIGH, the device processes 24 bit audio samples. When the AUXEN pin or "A4ON" register bit is LOW, the device processes 20 bit audio samples. On power up, the "A4ON" bit default is LOW. The GS9023 offers five predefined audio data input formats, selected via the AM[2:0] pins, which are listed in Table 2 and illustrated in Figure 1. The first four predefined formats relate to non-AES/EBU audio data while the fifth format corresponds to the AES/EBU audio format. The WCINA and WCINB pins should be grounded when inputting AES/EBU audio data as they are not used. 8
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GS9023
GENNUM CORPORATION
ACLK (128fs)
WCINA/B
SAFA/B VFLA/B UDA/B CSA/B
DATA
AIN-MODE0
MSB
23
LEFT CHANNEL
LSB
0
MSB 23
RIGHT CHANNEL
LSB
0
AIN-MODE1
RIGHT CHANNEL LSB
7 0
MSB
23
LEFT CHANNEL
8
LSB 0
MSB 23
RIGHT CHANNEL
8
AIN-MODE2
RIGHT CHANNEL LSB
5 0
MSB
23
LEFT CHANNEL
6
LSB 0
MSB 23
RIGHT CHANNEL
6
AIN-MODE3
LSB
0 4
LEFT CHANNEL
MSB
23 23
LSB 0
RIGHT CHANNEL
4
MSB 23 23
AIN-AES/EBU
LSB
0 3 4 7
LSB
8
AES/EBU Sub-frame format
Audio sample word
MSB
27 28 29 30 31 0
3
LSB 4
7
LSB 8
Audio sample word
MSB 27 28 29 30 31
Synchronization preamble
20bits 24bits Validity flag User data Channel status Parity bit
9
M M Channel 1 W Channel 2 B Channel 1 W
Channel 2
M
Channel 1
W Channel 2
Sub-frame Frame 0 (Start of Block)
Sub-frame Frame 2
Frame 1
Fig. 1: Audio Input Format Timing Diagram
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Audio Data Packets
The GS9023 can multiplex up to four audio channels. The channels are selectable via the "CHACT(4-1)" bits of Host Interface Register #1h. The audio group (Audio packet data ID) for each device is configured in "AD20ID[3:0]" of Host Interface Register #3h. On power up, the four audio channels and audio group 1 are selected by default. NOTE: Do not rely on default value. Reprogram on power up or reset. The "CASCADE" bit in Host Interface Register #4h controls the manner in which multiplexing is performed. When "CASCADE" is LOW, the GS9023 deletes all existing ancillary packets. New packets are multiplexed at the first location after the end of active video (EAV) in the horizontal ancillary space (HANC). See Figure 2.
When "CASCADE" is HIGH, the GS9023 multiplexes packets at the first free location in the horizontal ancillary (HANC) space after the end of active video (EAV) if there is sufficient space remaining to insert the packet. The GS9023 does not check if existing audio group samples are present in the video signal. Use caution in applications where the video signal contains existing audio packets to avoid adding identical group samples. See Figure 3. The GS9023 assumes that the ancillary space from the first free location is empty to the start of active video (SAV). Existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the HANC space or the insertion of a new audio data packet may overwrite existing data. See Figure 4.
GS9023
Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video Signal before GS9023
Audio Group 1 (New)
EAV
Empty
Video Signal after GS9023 Insertion of Audio Group 1 ("CASCADE" = LOW)
Fig. 2
Extended Audio Group 3
Extended Audio Group 4
Audio Group 3
Audio Group 4
EAV
Empty
Video Signal before GS9023
Extended Audio Group 3 (Old)
Extended Audio Group 4 (Old)
Extended Audio Group 3 (New)
Audio Group 3 (Old)
Audio Group 4 (Old)
Audio Group 3 (New)
EAV
Empty
Video Signal after GS9023 Insertion of Audio Group 3 ("CASCADE" = HIGH)
Fig. 3
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SAV
SAV
SAV
SAV
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Extended Audio Group 2
Audio Group 4
Audio Group 2
EAV
Empty
Empty
Video signal before GS9023
Audio Group 2 (Corrupted) (Old)
SAV
GS9023
Extended Audio Group 2 (Old)
Audio Group 4 (Old)
Audio Group 1 (New)
EAV
Empty
Video signal after GS9023 Insertion of Audio Group 1 ("CASCADE" = HIGH)
Fig. 4
In cases where an audio data packet does not fit inside the remaining HANC space, the audio packet is discarded. In this case, the "ADERR" bit of Host Interface Register #7h is HIGH indicating an audio packet multiplexing error. The error bit is cleared once accessed by the Host Interface. By cascading four GS9023 devices, it is possible to multiplex up to 16 audio channels (according to SMPTE 272) in a component video signal as shown in Figure 18. NOTE: In the 525/D1 video format, only 15 channels of 24 bit audio can be multiplexed. Cascade operation is not recommended with a composite video signal, as there is insufficient HANC space for more than four channels of audio. Audio packet insertion is not guaranteed in this case. The audio data packet structure as described in SMPTE 272M is shown in Figure 5. The audio data packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023. DID: Data ID. Audio data packets corresponding to an audio group are selected by programming "A20ID[3:0]" of Host Interface Register #3h for audio groups 1 to 4 as follows:
X X+1 X+2 X X+1 X+2 X
Group 1: Fh (2FFh) Group 2: Dh (1FDh) Group 3: Bh (1FBh) Group 4: 9h (2F9h) NOTE: The six most significant bits of the DID are internally generated by the GS9023. DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023. DC: Data Count. The data count represents the number of user data words to follow (maximum of 255 words). The data count is automatically generated by the GS9023. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023. The serial audio data samples, are mapped into three contiguous ancillary data words (X, X+1, X+2) as shown in Table 3.
X+1 X+2
X
X+1 X+2
X
X+1 X+2
X
AES 1, CH.1
AES 1, CH.1
AES 1, CH.2
AES 1, CH.2
AES 1, CH.2
AES 2, CH.1
AES 2, CH.1
AES 2, CH.1
AES 1, CH.2
AES 1, CH.2
AES 1, CH.2
AES 2, CH.1
AES 2, CH.1
AES 2, CH.1
AES 2, CH.2
SAV
X+1 X+2
AES 2, CH.2
AES 1, CH.1
AES 2, CH.2
ADF*
ADF*
ADF*
DBN
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Fig. 5: Audio Data Packet Structure with 4 Audio Channels, 1 Audio Group
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CS
TABLE 3: Audio Packet Data Sample Structure BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WORD X not b8 aud 5 aud 4 aud 3 aud 2 aud 1 aud 0 (LSB) ch 1 (MSB) ch 0 (LSB) Z WORD X+1 not b8 aud 14 aud 13 aud 12 aud 11 aud 10 aud 9 aud 8 aud 7 aud 6 WORD X+2 not b8 P C U V aud 19 (MSB) aud 18 aud 17 aud 16 aud 15
The audio packet data sample bits are defined as follows: Z: The Z flag is set HIGH at the same sample coincident with the beginning of a new AES channel status block (frame 0) and is otherwise set LOW. In non-AES/EBU data input formats this bit is set to the value of the SAFA/B input pins at the rising edge of WCINA/B. ch[1:0]: Identification of the channels in an audio group as shown in Table 4. aud[19:0]: Twos complement linearly represented audio data. The audio data is input from the AINA and AINB pins. V: AES/EBU sample validity bit. If the audio sample is valid the bit is set LOW. If the audio sample is invalid, the bit is set HIGH. In non-AES/EBU data input formats, this bit is set to the value of the VFLA/B input pins at the rising edge of WCINA/B. U: AES/EBU user bit. In non-AES/EBU data input formats, this bit is set to the value of the UDA/B input pins at the rising edge of WCINA/B. C: AES/EBU audio channel status bit. In non-AES/EBU data input formats this bit is set to the value of the CSA/B input pins at the rising edge of WCINA/B. P: Even parity for the 26 previous bits in the audio data sample (excludes b9 in the first and second words). NOTE: The P bit is not the same as the AES/EBU parity bit. This bit is automatically generated by the GS9023.
Extended Audio Data Packets
GS9023
TABLE 4: Channel Identification Within The Audio Groups CH 1 0 CH 0 0 GROUP 1 Channel 1 Channel 2 Channel 3 Channel 4 GROUP 2 Channel 5 Channel 6 Channel 7 Channel 8 GROUP 3 Channel 9 Channel 10 Channel 11 Channel 12 GROUP 4 Channel 13 Channel 14 Channel 15 Channel 16
0
1
1
0
1
1
The GS9023 can multiplex 20 or 24 bit audio samples. For 24 bit audio samples, the 20 MSBs of a 24 bit audio sample are contained in the audio data packets and the 4 LSBs are contained in an extended audio data packet as defined in SMPTE 272. The extended audio data packet is multiplexed immediately following the corresponding audio data packet. See Figure 6.
Audio Group 4
EAV
Empty
Video signal before GS9023
Extended Audio Group 2 (New)
Audio Group 4 (Old)
Audio Group 2 (New)
EAV
Empty
Video signal after GS9023 Insertion of Audio Group 2 & Extended Audio Group 2 ("CASCADE" = HIGH)
Fig. 6
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SAV
SAV
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AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
AES 1 CH.1/2
AES 2 CH.3/4
ADF*
ADF*
ADF*
DBN
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Fig. 7: Extended Audio Data Packet Structure
CS
GS9023
To select 24 bit audio operation, the user must set the AUXEN pin or the "A4ON" bit of Host Interface Register #1h HIGH. When the AUXEN pin or "A4ON" bit is HIGH, the GS9023 does not multiplex the audio data packet and the associated extended audio data packet if there is insufficient room for both in the HANC space. In this case, the "ADERR" bit of Host Interface Register #7h is set HIGH, indicating an audio packet multiplexing error. The error bit is cleared when accessed by the Host Interface. The audio group (Extended packet data ID) for each device is configured in "AD4ID[3:0]" of Host Interface Register #3h. On power up, audio group 1 is selected by default. By cascading four GS9023 devices, it is possible to multiplex up to 16 audio channels (according to SMPTE 272) in a component video signal as shown in Figure 18. NOTE: In the 525/D1 video format, only 15 channels of 24 bit audio can be multiplexed in the cascade configuration. The extended audio data packet structure as described in SMPTE 272M is shown in Figure 7. The extended audio data packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023. DID: Data ID. Extended audio data packets corresponding to an audio group are selected by programming "A4ID[3:0]" of Host Interface Register #3h for audio groups 1 to 4 as follows: Group 1: Eh (1FEh) Group 2: Ch (2FCh) Group 3: Ah (2FAh) Group 4: 8h (1F8h) NOTE: The six most significant bits of the DID are automatically generated by the GS9023. DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023.
DC: Data Count. The data count represents the number of user data words to follow (maximum of 255 words). The data count is automatically generated by the GS9023. DATA WORDS: The extended audio data samples are mapped into ancillary data words as shown in Table 5.
TABLE 5: Extended Audio Packet Data Sample Structure BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ANC DATA WORD not b8 a y3 (MSB) y2 y1 y0 (LSB) x3 (MSB) x2 x1 x0 (LSB)
The extended audio packet data sample bits are defined as follows: x[3:0]: Auxiliary data from subframe 1. y[3:0]: Auxiliary data from subframe 2. a: Address pointer. LOW for channels 1 and 2, and HIGH for channels 3 and 4. This bit is internally generated by the GS9023. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023.
Audio Control Packets
The audio control packet structure is detailed in SMPTE 272M. The audio group (Audio control packet data ID) for each device is configured in "ACID[3:0]" of Host Interface Register #4h. The Audio control parameters are configured in Host Interface Registers #Ah, #Bh, #Ch and #Dh. The audio control packet multiplexing positions for the various
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video standards are listed in Table 6. In a component video signal, a maximum of 4 audio control packets can be multiplexed in a cascade connection. On power up, audio group 1 is selected by default. The GS9023 determines if multiplexing is possible by searching for the first free location in the HANC space after the signal EAV and calculates if there is sufficient remaining space to insert the audio packet. Existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the HANC space or the insertion of a new audio data packet may overwrite existing data. In cases where an audio control data packet does not fit inside the remaining HANC space, the audio control packet is discarded. In this case, the "ACERR" bit of Host Interface Register #7h is HIGH indicating an audio control packet multiplexing error. The error bit is cleared when accessed by the Host Interface. The audio control packet structure as described in SMPTE 272M is shown in Figure 8.
TABLE 6: Multiplexing Positions for Audio Control Packets VIDEO STANDARD 525/D2 525/D1 525/16:9 525/4:4:4:4 625/D2 625/D1 625/16:9 625/4:4:4:4 625/4:2:2P MULTIPLEXING LINES 12/275 12/275 12/275 12/275 8/321 8/321 8/321 8/321 15/641 HORIZONTAL STARTING POSITION 795 1444 1924 2884 972 1444 2277 2884 1444 HORIZONTAL ENDING POSITION 849 1711 2283 3427 1035 1723 2299 3451 1723
GS9023
DELC0
DELC1
DELC2
DELD0
DELD1
DELD2
DELA0
DELA1
DELA2
DELB0
DELB1
DELB2
AF1-2
AF3-4
ADF*
ADF*
ADF*
RSRV
RSRV
DBN
RATE
ACT
DID
DC
* The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Fig. 8: Audio Control Packet Structure
The audio control packets words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023. DID: Data ID. Audio control packets corresponding to an audio group are selected by programming "ACID[3:0]" of Host Interface Register #4h for audio groups 1 to 4 as follows: Group 1: Fh (1EFh) Group 2: Eh (2EEh) Group 3: Dh (2EDh) Group 4: Ch (1ECh) NOTE: The six most significant bits of the DID are automatically generated by the GS9023. DBN: Data Block Number. The data block number is used when data blocks within a common data ID are to be linked or to distinguish consecutive data blocks within a common data ID. The data block number continuously increments from 1 to 255 and is generated automatically by the GS9023.
DC: Data Count. The data count represents the number of data words to follow. The data count has a fixed value of 212h and is automatically generated by the GS9023. AF1-2: Audio frame number for channels 1 and 2. AF3-4: Audio frame number for channels 3 and 4. For an audio sampling frequency of 48kHz, the audio frame numbers are sequenced from one to five for 525 line video standards and fixed at one for 625 line video standards. The audio frame numbers, AF1-2 and AF3-4, are automatically generated by the GS9023 and set to the same value. The sequence count is started at one at the first frame after `lock' is achieved. RATE: Sampling frequency. The GS9023 operates at a fixed sampling frequency of 48kHz. The audio control packet RATE word structure is shown in Table 7.
TABLE 7: Audio Control Packet Rate Word Structure BIT b9 b8 b7 RATE WORD not b8 not used (fixed to 0) y2 (MSB, fixed to 0)
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TABLE 7: Audio Control Packet Rate Word Structure BIT b6 b5 b4 b3 b2 b1 b0 RATE WORD y1 (fixed to 0) y0 (LSB, fixed to 0) bsync x2 (MSB, fixed to 0) x1 (fixed to 0) x0 (LSB, fixed to 0) async
TABLE 8: Audio Control Packet ACT Word Structure BIT b9 b8 b7 b6 b5 b4 b3 b2 ACT WORD not b8 p reserved (set to 0) reserved (set to 0) reserved (set to 0) reserved (set to 0) a4 a3 a2 a1
GS9023
The audio control packet RATE word bits are defined as follows: x[2:0], y[2:0]: Audio sampling rate for subframe 1 and 2 respectively. Fixed at 48kHz. async, bsync: Set LOW when each audio channel pair is operating synchronously and set HIGH when operating asynchronously. Forced LOW due to synchronous operation. ACT: The ACT word indicates the active group channels. The audio control packet ACT word structure is shown in Table 8.
b1 b0
The audio control packet ACT word bits are defined as follows: p: Even parity for bits b0 to b7. a(4-1): Individual active channel status indicator. The bits correspond directly to the "CHACT(4-1)" bits of Host Interface Register #1h. The bits are set HIGH for each active channel in a given audio group. The correlation of the active channels for the four active audio groups is shown in Table 9.
TABLE 9: Audio Control Packet Active Channel Configuration GROUP1 CHACT 1 CHACT 2 CHACT 3 CHACT 4 Channel 1 Channel 2 Channel 3 Channel 4 GROUP2 Channel 5 Channel 6 Channel 7 Channel 8 GROUP3 Channel 9 Channel 10 Channel 11 Channel 12 GROUP4 Channel 13 Channel 14 Channel 15 Channel 16
DELx(0-2): Indicates the amount of accumulated audio processing delay relative to video, measured in audio sample intervals for each of the channels. Positive values indicate that the video leads the audio. The audio control packets delay word structure is shown in Table 10.
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TABLE 10: Audio Control Packet Delay Structure BIT b9 b8 b7 b6 b5 b4 b3 b2 b1 DELx0 not b8 dela/b 7 dela/b 6 dela/b 5 dela/b 4 dela/b 3 dela/b 2 dela/b 1 dela/b 0 (LSB) e DELx1 not b8 dela/b 16 dela/b 15 dela/b 14 dela/b 13 dela/b 12 dela/b 11 dela/b 10 dela/b 9 DELx2 not b8 dela/b 25 (Sign) dela/b 24 (MSB) dela/b 23 dela/b 22 dela/b 21 dela/b 20 dela/b 19 dela/b 18
the user wants the arbitrary data packet to be multiplexed. The corresponding line in field 2 is automatically selected for arbitrary data packet multiplexing. Arbitrary data is typically multiplexed during the active portion of the line in the vertical blanking interval (VBI). Care should be taken to avoid selecting a line in the active picture. Table 11 lists recommended multiplexing lines according to the video standard. NOTE: In field #1, the line number is offset by one from the value configured in "PKTLINE[7:0]". Arbitrary data is input to the GS9023 as shown in Figure 9. The data is stored in an internal arbitrary data packet buffer which is cleared at the end of every field. Arbitrary data must be written to the buffer before the line number specified in "PKTLINE[7:0]" is reached in order for the packet to be multiplexed. Data is input to the PKT[8:0] pins and clocked in on the rising edge of PCLK. PKTEN must be set HIGH one PCLK cycle before the data at the PKT[8:0] inputs is valid. PKTEN must go LOW one PCLK cycle before the last user data word (UDW) is input to the PKT[8:0] inputs. Parity (bit 8) for each UDW can be enabled by setting the "PKTPRTY" bit of Host Interface Register #8h to HIGH. When "PKTPRTY" is HIGH, data input at PKT[8] is overwritten by the parity bit. Up to 255 words (253 UDWs + SDID + DC) can be input and multiplexed once per field. The arbitrary data packet structure as described in SMPTE 291M is shown in Figure 9.
GS9023
b0
dela/b 8
dela/b 17
The audio control packet delay word bits are defined as follows: e: Indicates valid audio delay data when set HIGH. Corresponds to the "ACDLY" bit of Host Interface Register #Dh. dela/b[25:0]: The audio channel pair delay is programmed in bits "DELA/B[25:0]" of Host Interface Register #Ah, #Bh, #Ch and #Dh. DELA[25:0] corresponds to the delay for channels 1 and 2. "DELB[25:0]" corresponds to the delay for channels 3 and 4. RSRV: Reserved. The word is fixed at 200h and is automatically generated by the GS9023. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023.
Arbitrary Data Packets
The GS9023 is capable of multiplexing arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code data (LTC), vertical interval time code data (VITC) or other data which is multiplexed once per field. The user must input the 9 LSBs starting from the secondary data identification (SDID) word to the last user data word (UDW) of the ancillary data packet containing arbitrary data. The CS word and bit 10 of all words in the packet are internally generated. The arbitrary data packet data ID is configured in "PKTID[7:0]" of Host Interface Register #5h. To process arbitrary data, the user must set the "PKON" bit of Host Interface Register #1h. Also, the user must specify the line number in "PKTLINE[7:0]" in Host Interface Register #9h. This value corresponds to the line in video field 1 in which 16
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TABLE 11: Multiplex Position For Arbitrary Data Packet VIDEO STANDARD 525/D2 525/D1 525/16:9 RECOMMENDED MULTIPLEX LINE 9/272 14/277 14/277 HORIZONTAL STARTING POSITION (WORD #) 340 0 0 HORIZONTAL ENDING POSITION (WORD #) 360 1439 1919
GS9023
NOTE: 525/4:4:4:4 and all 625 line video standards are not supported. * Horizontal Starting Position 0 is the first word of the active picture.
1 clk
1 clk
PCLK (I) PKTEN (I) PKT[8:0] (I) Valid data
ADF 1,2
ADF 1,2
ADF 1,2
DID 2
SDID
UDW
UDW
UDW
UDW
UDW
UDW
NOTE: 1 - The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M). 2 - The ADF, DID and CHKSUM words are automatically generated by the GS9023.
Fig. 9: Arbitrary Data Packet Input Timing Diagram
The arbitrary data packet words are defined as follows: ADF: Ancillary Data Flag. The ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the GS9023. DID: Data ID. Configured in "PKTID[7:0]" of Host Interface Register #5h. The two most significant bits are internally generated by the GS9023. SDID: Secondary Data ID. The Secondary Data ID is handled as user input data. DC: Data Count. The data count represents the number of user data words to follow, up to a maximum of 255 words. The data count is handled as user input data. For the GS9023 the maximum data count is 253 since the total number of words that can be input is 255 less the SDID and DC words. UDW: User Data Word. CS: Checksum. The checksum consists of nine bits. The checksum is used to determine the validity of the words data ID through user data. It is the sum of the nine least significant bits of the words data ID through user data. The checksum is automatically generated by the GS9023.
Error Detection
The GS9023 provides error status information in Host Interface Register #7h as described in Table 14. All errors are cleared when Host Interface Register #7h is read.
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UDW
CS 2
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DC
DEMULTIPLEX MODE Video Clock Input
A master video clock must be supplied to the PCLK pin corresponding to the selected video signal. The supported video input standards and corresponding clock frequencies are listed in Table 1.
Video Data Input
The video data DIN[9:0] is clocked in to the GS9023 on the rising edge of PCLK. The video clock frequency must correspond to the video input standard selected. This can be done with the VM[2:0] and TRS input pins or selected via the "VSEL" bit of Host Interface Register #0h. When "VSEL" is set HIGH, the video input standard is selected by "VMOD[2:0]" and "D2_TRS" in Host Interface Register #0h. The supported video input standards are listed in Table 1. After the user has specified the video input standard via the VM[2:0] and TRS pins or in Host Interface Register #0h, the GS9023 performs video standard detection to verify that the input video stream corresponds to the selected standard. When the selected video input standard is verified, the "VXST" bit of Host Interface Register #0h is set HIGH. The GS9023 then performs a `lock' procedure, as selected by the "ACTSEL" bit of Host Interface Register #4h, to determine if the audio is synchronous to the video. When "ACTSEL" is LOW, the GS9023 counts the number of audio samples present in a frame or multiple frames, depending on the video standard selected. `Lock' is achieved if the required number of samples are detected for 48kHz synchronous audio. When "ACTSEL" is HIGH, the GS9023 `locks' by detecting the presence of an audio control packet corresponding to the DID configured in "ACID[3:0]" of Host
Interface Register #4h and occurring at the expected line and position as listed in Table 6. If the video signal does not contain audio control packets, `lock' will not occur. Once `lock' is achieved the LOCK output pin and the "LOCK" bit of Host Interface Register #0h are set HIGH and audio demultiplexing begins. The LOCK output pin and the "LOCK" bit stay active regardless of the number of samples in the video stream after `lock' is achieved. The GS9023 drops out of `lock' when there are no more packets detected in the video stream.
Video Data Output
GS9023
The video signal is output at the DOUT[9:0] pins. The video signal is synchronized to the rising edge of PCLK. The GS9023 is capable of removing audio, extended audio, arbitrary and audio control packets from the video stream. To remove packets, the user must set the ANCI pin HIGH or set the "VSEL" and "ADEL" bits of Host Interface Register #0h HIGH. The GS9023 then removes each packet having a DID corresponding to either the audio DID, the extended audio DID or the arbitrary data DID stored in the Host Interface Registers from the video stream. See Figure 10. NOTE: The GS9023 passes EDH packets through unchanged in the Demultiplex Mode. If any audio, extended audio, arbitrary or audio control packets are deleted by the GS9023, the EDH CRC words become invalid. When the ANCI pin or "ADEL" bit is LOW, all ancillary data packets remain in the video signal. See Figure 11. TRS can also be removed from a 525/625 D2 video signal when the TRS pin is set HIGH or the "VSEL" and "D2_TRS" bits of Host Interface Register #0h are set HIGH.
Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video signal before GS9023
Extended Audio Group 2 (Old)
Audio Group 2 (Old)
EAV
Empty
Empty
Video signal after GS9023 Removal of Audio Group 1 & Extended Audio Group 1 (ANCI = HIGH or "VSEL" and "ADEL" = HIGH)
Fig.10
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SAV
SAV
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Extended Audio Group 1
Extended Audio Group 2
Audio Group 1
Audio Group 2
EAV
Empty
Video signal before GS9023
SAV
GS9023
Audio Group 1 (Old)
Extended Audio Group 2 (Old)
Extended Audio Group 1 (Old)
Audio Group 2 (Old)
EAV
Empty
Video signal after GS9023 Removal of Audio Group 1 & Extended Audio Group 1 (ANCI = LOW or "VSEL" = HIGH and "ADEL" = LOW)
Fig. 11 Audio Clock Input TABLE 12: Audio Output Formats FORMATS AOUT-MODE 0 WCOUT Active 48kHz Active 48kHz Active 48kHz Active 48kHz AM[2] 0 AM[1] 0 AM[0] 0
The user must input a master audio clock (128 fs: 6.144MHz) at the ACLK clock terminal. This clock must be synchronized with the video signal input to the GS9023. The audio word clock inputs WCINA and WCINB must be grounded.
Audio Data Output
AOUT-MODE 1
0
SAV
0
1
AOUT-MODE 2
0
1
0
The serial audio data for channels 1 and 2 are output at the AOUTA pin. The serial audio data for channels 3 and 4 are output at the AOUTB pin. Both outputs are synchronized to the rising edge of ACLK. The GS9023 can demultiplex 20 or 24 bit audio data samples. When 24 bit audio samples are detected, the AUXEN pin and bit "A4ON" of Host Interface Register #1h are set HIGH. When 20 bit audio samples are detected the AUXEN pin and "A4ON" register bit are set LOW. When AUXEN and "A4ON" are LOW, bits 4-7 of the AES/EBU output data format are set to "0". In the non-AES/EBU formats, bits 0-3 are set to "0". See Figure 12. The GS9023 offers five predefined audio data output formats, selected via the AM[2:0] pins, which are listed in Table 12 and illustrated in Figure 12. The first four predefined formats relate to non-AES/EBU audio data while the fifth format corresponds to the AES/EBU audio format. During reset, the audio outputs are forced LOW. The GS9023 supports muting of the audio data outputs. The output serial audio samples are forced to zero when the MUTE pin or "MUTE" bit of Host Interface Register #4h are set HIGH. The audio data outputs are also muted when there is no video input signal.
AOUT-MODE 3
0
1
1
AOUT-AES/EBU Not Used Not Used Not Used
1 1 1 1
0 0 1 1
0 1 0 1
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GS9023
GENNUM CORPORATION
ACLK (128fs)
WCOUT
SAFA/B VFLA/B UDA/B CSA/B
AOUT-MODE0
MSB
23
DATA
LEFT CHANNEL
LSB
0
MSB 23
RIGHT CHANNEL
LSB
0
AOUT-MODE1
RIGHT CHANNEL LSB
7 0
MSB
23
LEFT CHANNEL
8
LSB 0
MSB 23
RIGHT CHANNEL
8
AOUT-MODE2
RIGHT CHANNEL LSB
5 0
MSB
23
LEFT CHANNEL
6
LSB 0
MSB 23
RIGHT CHANNEL
6
AOUT-MODE3
LSB
0 4
LEFT CHANNEL
MSB
23 23
LSB 0
RIGHT CHANNEL
4
MSB 23 23
AOUT-AES/EBU
LSB
0 3 4 7
LSB
8
AES/EBU Sub-frame format
Audio sample word
MSB
27 28 29 30 31 0
3
LSB 4
7
LSB 8
Audio sample word
MSB 27 28 29 30 31
Synchronization preamble
20bits 24bits Validity flag User data Channel status Parity bit
20
M M Channel 1 W Channel 2 B Channel 1 W
Channel 2
M
Channel 1
W Channel 2
Sub-frame Frame 0 (Start of Block)
Sub-frame Frame 2
Frame 1
Fig. 12: Audio Data Output Formats
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Control Code Output
In the non-AES/EBU output formats, the V, U and C bits are output separately from the audio data stream. The bits are output respectively to the VFLA/B, UDA/B and CSA/B pins according to the channel pair to which they belong and change state on the rising edge of WCOUT. The SAFA/B output pins are set to HIGH for one audio frame out of 192 frames to mark the start of a block. In the AES/EBU audio output format, the respective pins are not used.
Detection of Audio Packets
extended audio packets are found on the active video line, the AUXEN pin and "A4ON" bit are set to LOW. On power up, audio group 1 extended audio packets are selected by default.
Detection of Audio Control Packets
The GS9023 can demultiplex up to four audio channels of an audio group. The audio group (Audio packet data ID) for each device is configured in "AD20ID[3:0]" of Host Interface Register #3h. When the corresponding audio packets are found on the active video line, the GS9023 sets the respective "CHACT(4-1)" bits of Host Interface Register #1h. If no corresponding audio packets are found on the active video line, the "CHACT(4-1)" bits are set LOW. By connecting four GS9023 devices in parallel, it is possible to demultiplex up to 16 audio channels in a component video signal as shown in Figure 19. On power up, audio group 1 is selected by default.
Detection of Extended Audio Packets
The audio group (Audio control packet data ID) for each device is configured in "ACID[3:0]" of Host Interface Register #4h. When the configured ID is detected on the designated video lines (see Table 6), the "ACON" bit of Host Interface Register #1h is set. The corresponding Audio control parameters are stored in Host Interface Registers #Ah, #Bh, #Ch and #Dh. If an audio control packet is not detected or found in non-designated video lines, "ACON" is set to LOW. However, the information in the audio control packets found in non-designated lines is considered valid and is stored in Host Interface Registers #Ah, #Bh, #Ch and #Dh. On power up, audio group 1 audio control packets are selected by default.
Detection and Output of Arbitrary Data Packets
GS9023
The GS9023 can demultiplex 20 or 24 bit audio samples. For 24 bit audio samples, the 20 MSBs of a 24 bit audio sample are contained in the audio data packets and the 4 LSBs are contained in an extended audio data packet as defined in SMPTE 272. The audio group (Extended packet data ID) for each device is configured in "AD4ID[3:0]" of Host Interface Register #3h. When the corresponding extended audio packets are detected on the active video stream, the GS9023 sets the AUXEN pin and the "A4ON" bit of Host Interface Register #1h to HIGH. If no corresponding
The GS9023 is capable of demultiplexing arbitrary data packets according to SMPTE 291M. There are no limitations on the number of packets that can be demultiplexed and the packets can be located outside of the vertical blanking interval (VBI). The arbitrary data packet data ID is configured in PKTID[7:0] of Host Interface Register #5h. When the configured ID is detected in the active video or HANC area, data on the PKT[8:0] pins is clocked out on the rising edge of PCLK. The GS9023 sets the PKTEN output pin HIGH, when the data at the PKT[8:0] outputs is valid. PKTEN is set LOW when the last user data word (UDW) is output from PKT[8:0]. Figure 13 shows the output timing.
1 clk
PCLK (I) PKTEN (O) PKT[8:0] (O) Valid data
X+(N-2)
X+(N-1)
NOTE: 1 - The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M) and three words in component systems (ANSI/SMPTE 125M).
Fig. 13: Arbitrary Data Output Timing Diagram Error Detection
The GS9023 provides error status information in Host Interface Registers #7h, #8h and #9h as described in Table 15. Register #7 contains error information on audio sampling and CRC conditions. Register #8 contains error 21
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information on audio packet data block number and data count. Register #9 contains error information on Control packets. Errors are cleared when the respective Host Interface Register is read.
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CHKSUM
ADF 1
ADF 1
ADF 1
SDID
DID DID
X+N
X+1
X+2
X+3
DC
X
MULTIPLEX AND DEMULTIPLEX MODES Delay of Video and Audio
The GS9023 can be configured for various audio sample delays with respect to the video signal. The audio sample delay is selected in "BUFSEL[1:0]" of Host Interface Register #6h. Table 13 lists the various audio sample delays.
TABLE 13: Audio Video Delay "BUFSEL[1:0]" 0 1 MODE (70 Sample) (26 Sample Default) (20 Sample) MULTIPLEX (us) 875 250 DEMULTIPLEX (us) 541 312 MULTIPLEX/DEMULTIPLEX CONNECTION (us) 1416 563
GS9023
2
187
250
437
NOTE: When the video signal is in D2 format, the delay is fixed at 70 samples (1416 us).
Host Interface
Non-Standard Sample Distributions
The Host Interface Registers allow for device configuration and provide status information. The GS9023 contains sixteen internal registers that are accessible through the Host Interface. Based on the mode of operation the registers have different functionality. In Multiplex Mode the registers are defined in Table 14 and in Demultiplex Mode the registers are defined in Table 15. The asynchronous Host Interface consists of a 4 bit address bus (ADDR[3:0]), 8 bit data bus (DATA[7:0]), read enable (RE), write enable (WE) and chip select (CS). The Host Interface access is independent of the PCLK or ACLK inputs. Read and write cycle timing is detailed in Figure 16. In a read cycle, CS is driven LOW tAS seconds after a valid address. RE is then driven LOW after tACS seconds for a minimum of tRD seconds. After tGQV seconds, the address register contents are output on the data bus. After a minimum of tRDH seconds, CS is driven HIGH to end the cycle. Similarly, in a write cycle, CS is driven LOW tAS seconds after a valid address. WE is then driven low after tACS seconds for a minimum of tWD seconds. Valid data must be present for a minimum of tDS seconds before WE is driven HIGH again. After a minimum of tWDH seconds, CS is driven HIGH to end the cycle.
Reset
Gennum Corporation has made every effort to maximize compatibility of the GS9023 with other Embedded Audio data streams. Unfortunately, due to variations in implementations (i.e. non-standard sample distributions) Gennum cannot guarantee compatibility with all Embedded Audio data streams.
Interconnection with GS9032 or GS7005
The user should pay special attention when laying out the GS9023 to operate with the GS9032 or GS7005. The MSB to LSB convention is consistent between the GS9023 and GS9022 but reversed with respect to the GS9032 or GS7005. Layout complexity can be minimized by placing the GS9023 and the GS9032 or GS7005 on opposite sides of the printed circuit board (PCB).
Reset timing is detailed in Figure 17. Setting the RESET pin to LOW for a period of tRESET seconds forces the audio outputs LOW and re-initializes the internal control circuitry including returning all Host Interface Register values to their original default values. The RESET pin can be used for synchronizing multiple devices. 22
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TABLE 14: Multiplex Mode Host Interface Registers ADDRESS 0h BIT 2-0 NAME VMOD[2:0] FUNCTION Video standard selection. See Table 1. Valid when "VSEL" is HIGH. Used in conjunction with "D2_TRS". "VMOD[2]" is the MSB and "VMOD[0]" is the LSB. Lock indicator. Same functionality as the LOCK pin. When set HIGH, the video standard has been identified, the start of a new video frame has been detected and the device is ready to multiplex audio. NOTE: LOCK will not be set HIGH unless at least one of the "CHACT(4-1)" bits (Address #1h) is HIGH. 4 EDHDEL EDH data delete. When set LOW, existing EDH packets are removed from the video stream. When set HIGH, existing EDH packets are passed through unless overwritten via the EDH_INS pin or the "EDHON" bit. Valid only when "CASCADE" (Address #4h bit 7) is LOW. Video signal detection flag. Set HIGH when the video signal corresponds to standard selected on the VM[2:0] and TRS pins or with the "VMOD[2:0]" and "D2_TRS" bits. TRS select. Same functionality as the TRS pin. Used to select video standard format.When set HIGH, TRS is added to a composite video signal. Valid only when "VSEL" is HIGH. Used in conjunction with "VMOD[2:0]". Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[2:0] and TRS pins. When set HIGH, the video input format is configured via the "VMOD[2:0]" and "D2_TRS" bits. Audio channel enable. When set HIGH, the corresponding audio channel is multiplexed into the video signal. "CHACT(4)" is the MSB and "CHACT(1)" is the LSB. NOTE: Do not rely on default value. Reprogram on power up or reset. 4 5 ACON EDHON Audio Control packet enable. When HIGH, the audio control packet is multiplexed in the video signal. EDH packet enable. Same functionality as the EDH_INS pin. When set HIGH, the GS9023 performs EDH functions according to SMPTE RP165. NOTE: Active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in Host Interface Registers #Eh and #Fh. 6 A4ON Extended audio packet enable. Same functionality as the AUXEN pin. When set HIGH, the extended audio packet is multiplexed in the video signal (24 bit audio). Arbitrary data packet enable. When set HIGH, an arbitrary data packet is multiplexed in the video signal. Not used. Designates the 4 LSBs of the audio data packet DID word. The 6 MSBs are internally generated. "AD20ID[3]" is the MSB and "AD20ID[0]" is the LSB. Designates the 4 LSBs of the extended audio data packet DID word. The 6 MSBs are internally generated. "AD4ID[3]" is the MSB and "AD4ID[0]" is the LSB. R/W 0 R/W R/W 0 0 R/W 0 R/W R/W DEFAULT 0
3
LOCK
R
0
GS9023
5
VXST
R
0
6
D2_TRS
R/W
0
7
VSEL
R/W
0
1h
3-0
CHACT(4-1)
R/W
Fh
7 2h 3h 7-0 3-0 7-4
PKON RSV AD20ID[3:0] AD4ID[3:0]
R/W R/W R/W
0
Fh Eh
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TABLE 14: Multiplex Mode Host Interface Registers (Continued) ADDRESS 4h BIT 3-0 4 5 6 NAME ACID[3:0] RSV MUTE AC34/12 FUNCTION Designates the 4 LSBs of the audio control packet DID word. The 6 MSBs are internally generated. "ACID[3]" is the MSB and "ACID[0]" is the LSB. Not used. Audio mute enable. Same functionality as the MUTE pin. When set HIGH, the multiplexed audio and extended data packets are forced to zero. Audio control packet channel pair select. When set HIGH, audio control packet delay data for audio channels 3 and 4 is captured in registers Ah, Bh, Ch and Dh. When set LOW, audio control packet delay data for audio channels 1 and 2 is captured in registers #Ah, #Bh, #Ch and #Dh. Cascade select. When set HIGH, the GS9023 device is part of a cascaded architecture. New packets are multiplexed into the video signal starting at the first free location of the HANC space if there is sufficient remaining space to insert the packet. When set LOW, new packets are multiplexed into the video signal starting after EAV. Existing ancillary data packets are overwritten and the remaining ancillary space is cleared. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "PKTID[7]" is the MSB and "PKTID[0]" is the LSB. Video/audio delay mode. "BUFSEL[1]" is the MSB and "BUFSEL[0]" is the LSB. See Table 13. Not used. Audio data packet multiplexing error. The packet will not be multiplexed because of insufficient room in the HANC space. Error is cleared when read. Audio control packet multiplexing error. The packet will not be multiplexed because of insufficient room in the HANC space. Error is cleared when read. Not used. Not used. Arbitrary data packet parity select. When set HIGH, a parity bit is generated for every user data word (UDW) of an arbitrary data packet. This overwrites any data input at the PKT[8] pin. Not used. Audio CH1/2 detection flag. When set HIGH, an audio signal has been detected. Audio CH3/4 detection flag. When set HIGH, an audio signal has been detected. Arbitrary data packet insertion line. Designates the horizontal line on which the GS9023 can multiplex arbitrary data packets in the video signal. Audio control packet delay. Designates the audio control packet delay data as specified in the SMPTE 272M standard. "DELA" corresponds to audio channels 1 and 2, while "DELB" corresponds to audio channels 3 and 4. "DELA/B[25]" is the MSB and "DELA/B[0]" is the LSB. R/W R/W R/W R/W 0 DEFAULT Fh
GS9023
0
7
CASCADE
R/W
0
5h 6h
7-0 1-0 7-2
PKTID[7:0] BUFSEL[1:0] RSV ADERR ACERR RSV RSV PKTPRTY
R/W R/W R R R/W
0 0
7h
0 1 7-2
0 0
8h
0 1
0
5-2 6 7 9h Ah Bh Ch Dh 7-0 7-0 7-0 7-0 1-0 2
RSV AXST1/2 AXST3/4 PKTLINE[7:0] DELA/B[7:0] DELA/B[15:8] DELA/B[23:16] DELA/B[25:24] ACSYNCA/B
R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0
Audio control packet synchronization data. Designates the sync mode bits (asx, asy), as defined in SMPTE 272M (Section 14.5), of channels 1/2 or 3/4 of the audio control packet. The bits are selected by "AC34/12" in register #4h. Audio control packet delay active. Designates the `e' bit of word "DELx0" of an audio control packet as defined in SMPTE 272 (Section 14.7). When set HIGH indicates valid audio delay data. Not used.
R/W
3
ACDLY
R/W
0
7-4
RSV
-
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TABLE 14: Multiplex Mode Host Interface Registers (Continued) ADDRESS Eh BIT 0 1 2 3 4 7-5 Fh 0 1 2 3 4 5 6 7 NAME ANCI_EDH ANCI_EDA ANCI_IDH ANCI_IDA ANCI_UES RSV CRCEDH_A/B CRCEDA_A/B CRCIDH_A/B CRCIDA_A/B CRCUES_A/B CRCVLD_A/B RSV FF/AP_A/B FUNCTION EDH packet ancillary error flag. Error detected here. EDH packet ancillary error flag. Error detected already. EDH packet ancillary error flag. Internal error detected here. EDH packet ancillary error flag. Internal error detected already. EDH packet ancillary error flag. Unknown error status. Not used. EDH packet error flag. "CRCEDH_A" represents Full Field information. "CRCEDH_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCEDA_A" represents Full Field information. "CRCEDA_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCIDH_A" represents Full Field information. "CRCIDH_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCIDA_A" represents Full Field information. "CRCIDA_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet error flag. "CRCUES_A" represents Full Field information. "CRCUES_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). EDH packet CRC valid flag. "CRCVLD_A" represents Full Field information. "CRCVLD_B" represents Active Picture information. See "FF/AP_A/B" (bit 7). Not used. Full Field/Active Picture select. When set HIGH, the FF (Full Field) information is displayed in the above mentioned bits. When set LOW, the AP (Active Picture) information is displayed. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 DEFAULT 0 0 0 0
GS9023
0
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TABLE 15: Demultiplex Mode Host Interface Registers ADDRESS 0h BIT 2-0 NAME VMOD[2:0] FUNCTION Video standard selection. See Table 1. Valid when "VSEL" is HIGH. Used in conjunction with "D2_TRS". "VMOD[2]" is the MSB and "VMOD[0]" is the LSB. Lock indicator. Same functionality as the LOCK pin. When set HIGH, the video standard has been identified, the `lock' process selected by "ACTSEL" has been validated and the device is ready to demultiplex audio. See "ACTSEL" description. Ancillary data delete. Same functionality as the ANCI pin. When set HIGH, each ancillary data packet with a DID corresponding to either the audio packet DID, the extended audio packet DID or the arbitrary packet DID is removed from the video signal. When the "ADEL" bit is LOW, all ancillary data packets remain in the video signal. Valid only when "VSEL" is HIGH. Video signal detection flag. Set HIGH when the video signal corresponds to standard selected on the VM[2:0] and TRS pins or with the "VMOD[2:0]" and "D2_TRS" bits. TRS select. Same functionality as the TRS pin. Used to select video standard format. When set HIGH, TRS is removed from a composite video signal. Valid only when "VSEL" is HIGH. Used in conjunction with "VMOD[2:0]". Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[2:0] and TRS pins. When set HIGH, the video input format is configured via the "VMOD[2:0]" and "D2_TRS" bits. Active audio channel flags. When set HIGH, the corresponding audio packets have been detected on the active video line. When set LOW, no corresponding audio packets have been detected on the active video line. The flags are updated on every video line. Audio Control packet flag. When set HIGH, the audio control packet has been detected in the video signal. EDH flag. When set HIGH, EDH data has been detected in the video signal. Extended audio packet flag. When set HIGH, the extended audio packet has been detected on the active video line (24 bit audio). When set LOW, no extended audio packet has been detected on the active video line (24 bit audio). Not used. Not used. Designates the 4 LSBs of the audio data packet DID word. The 6 MSBs are internally generated. "AD20ID[3]" is the MSB and "AD20ID[0]" is the LSB. Designates the 4 LSBs of the extended audio data packet DID word. The 6 MSBs are internally generated. "AD4ID[3]" is the MSB and "AD4ID[0]" is the LSB. R/W R/W DEFAULT 0
3
LOCK
R
0
GS9023
4
ADEL
R/W
0
5
VXST
R
0
6
D2_TRS
R/W
0
7
VSEL
R/W
0
1h
3-0
CHACT(4-1)
R
0
4 5 6
ACON EDHON A4ON
R R R
0 0 0
7 2h 3h 7-0 3-0
RSV RSV AD20ID[3:0]
R/W Fh
7-4
AD4ID[3:0]
R/W
Eh
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TABLE 15: Demultiplex Mode Host Interface Registers (Continued) ADDRESS 4h BIT 3-0 NAME ACID[3:0] FUNCTION Designates the 4 LSBs of the audio control packet DID word. The 6 MSBs are internally generated. "ACID[3]" is the MSB and "ACID[0]" is the LSB. Not used. Audio mute enable. Same functionality as the MUTE pin. When set HIGH, the demultiplexed audio and extended packet data are forced to zero. Audio lock process select. When set HIGH, the GS9023 `locks' by detecting the presence of an audio control packet corresponding to the DID configured in "ACID[3:0]" and occurring at the expected line and position as listed in Table 6. When set LOW, the GS9023 `locks' by counting the number of audio samples in a frame or multiple frames and validating the number of samples detected based on the video standard. Not used. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "PKTID[7]" is the MSB and "PKTID[0]" is the LSB. Video/audio delay mode. "BUFSEL[1]" is the MSB and "BUFSEL[0]" is the LSB. See Table 13. AES/EBU CRC select. When set HIGH, the C bit (channel status information) of each audio sample contains CRC information as defined in the AES3-1992 standard. Not used. Not used. Sample error. Incorrect number of audio samples detected. 8008 audio samples (48kHz) in 5 video frames for a 525 line video format. 1920 audio samples (48kHz) in 1 video frame for a 625 line video format. Audio channel 1/2 CRC error. Audio channel 3/4 CRC error. Audio packet DBN error. A DBN discontinuity was detected. Audio packet DC error. The number of UDW indicated does not match the number of words found in the data packet. Not used. Audio packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the audio packet. Not used. Audio control packet DBN error. A DBN discontinuity was detected. NOTE: When a DBN discontinuity is detected, the VFLA/B pins remain valid (LOW). 1 3-2 4 6-5 7 ACCDCERR RSV ACCB9ERR RSV A4B9ERR Audio control packet DC error. The number of UDW indicated does not match the number of words found in the audio control packet. Not used. Audio control packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the audio control packet. Not used. Extended audio packet inversion bit error. An incorrect bit 9 inversion of bit 8 was detected in the extended audio packet. R R R 0 0 0 R/W R/W DEFAULT Fh
4 5
RSV MUTE
R/W 0
GS9023
6
ACTSEL
R/W
0
7 5h 7-0
RSV PKTID[7:0]
R/W 0
6h
1-0 2
BUFSEL[1:0] CRCADD
R/W R/W
1h 0
7-3 7h 4-0 5
RSV RSV SAMPERR
R 0
6 7 8h 0 1 2 3 7-4 9h 0
ACRCERR1/2 ACRCERR3/4 A20DBNERR A20DCERR RSV A20B9ERR RSV ACCDBNERR
R R R R R R
0 0 0 0
0
0
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TABLE 15: Demultiplex Mode Host Interface Registers (Continued) ADDRESS Ah Bh Ch Dh BIT 7-0 7-0 7-0 1-0 2 NAME DELA/B[7:0] DELA/B[15:8] DELA/B[23:16] DELA/B[25:24] ACSYNCA/B Audio control packet synchronization data. Designates the sync mode bits (asx, asy) as defined in SMPTE 272M (section 14.5) of channels 1/ 2 or 3/4 of the audio control packet. The bits are selected by "AC34/ 12". Audio control packet delay active. Designates the `e' bit of word "DELx0" of an audio control packet as defined in SMPTE 272 (section 14.7). When HIGH indicates valid audio delay data. Active channel 1/2 flag. Active channel 3/4 flag. Not used. Audio control packet channel pair select. When set HIGH, audio control packet delay data for audio channels 3 and 4 is captured in registers #Ah, #Bh, #Ch and #Dh. When set LOW, audio control packet delay data for audio channels 1 and 2 is captured in registers Ah, Bh, Ch and Dh. AES/EBU channel 1/2 Consumer/Professional status. See AES-3 1992 standard. AES/EBU channel 1/2 normal/non-audio status. See AES-3 1992 standard. AES/EBU channel 1/2 emphasis status. "EMPH1/2[2]" is the MSB and "EMP1/2[0]" is the LSB. See AES-3 1992 standard. AES/EBU channel 1/2 sync status. See AES-3 1992 standard. AES/EBU channel 1/2 frequency select status. "FSEL1/2[1]" is the MSB and "FSEL1/2[0]" is the LSB. See AES-3 1992 standard. AES/EBU channel 3/4 Consumer/Professional status. See AES-3 1992 standard. AES/EBU channel 3/4 normal/non-audio status. See AES-3 1992 standard. AES/EBU channel 3/4 emphasis status. "EMPH3/4[2]" is the MSB and "EMP3/4[0]" is the LSB. See AES-3 1992 standard. AES/EBU channel 3/4 sync status. See AES-3 1992 standard. AES/EBU channel 3/4 frequency select status. "FSEL3/4[1]" is the MSB and "FSEL3/4[0]" is the LSB. See AES-3 1992 standard. FUNCTION Audio control packet delay. Designates the audio control packet delay data as specified in the SMPTE 272M standard. DELA corresponds to audio channels 1 and 2, while DELB is the corresponds to audio channels 3 and 4. "DELA/B[25]" is the MSB and "DELA/B[0]" is the LSB. R/W R R R R R DEFAULT 0 0 0 0
GS9023
0
3
ACDLY
R
0
4 5 6 7
ACT1/2 ACT3/4 RSV AC34/12
R R R/W
0 0
0
Eh
0 1 4-2 5 7-6
CONPRO1/2 AUDMOD1/2 EMPH1/2[2:0] SYNC1/2 FSEL1/2[1:0] CONPRO3/4 AUDMOD3/4 EMPH3/4[2:0] SYNC3/4 FSEL3/4[1:0]
R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0
Fh
0 1 4-2 5 7-6
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ABSOLUTE MAXIMUM RATINGS
PARAMETER I/O Supply Voltage Internal Supply Voltage Input Voltage (any input) Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 sec.) VALUE -0.3 to 7.0V -0.3 to 4.0V -0.3 to VDDIO + 0.5V
GS9023
0C to 70C -65C to 150C 230C
DC ELECTRICAL CHARACTERISTICS
TA = 0C to 70C unless otherwise shown.
PARAMETER I/O Supply Voltage I/O Supply Current
SYMBOL VDDIO IDDIO
CONDITIONS 5V Operating range VDDIO = 5V; PCLK = 54.0 MHz
MIN 4.75
TYP 5.00 25
MAX 5.25
UNITS V mA
I/O Supply Current
IDDIO
VDDIO = 5V; PCLK = 27.0 MHz
18
mA
I/O Supply Voltage Internal Supply Voltage Internal Supply Current Internal Supply Current Input Current Hi-Z Output Leakage Current Output Voltage, Logic High Output Voltage, Logic Low Input Voltage, Logic High
VDDIO VDDINT IDDINT IDDINT IN OZ VOH VOL VIH
3.3V Operating range
3.00 3.00
3.30 3.30 67 37
3.60 3.60
V V mA mA
PCLK = 54.0 MHz PCLK = 27.0 MHz -1 -1 OH = -3mA OL = 3mA VDDIO = Max (5.25V or 3.6V) VDDIO = Min. (4.75V or 3.0V) = 1MHz, VDDIO = 0V = 1MHz, VDDIO = 0V = 1MHz, VDDIO = 0V VDDIO - 0.4 2.0
-
1 1 0.4 -
A A V V V
Input Voltage, Logic Low
VIL
-
-
0.8
V
Input Capacitance Output Capacitance I/O Capacitance
CI CO CIO
-
-
10 10 10
pF pF pF
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AC ELECTRICAL CHARACTERISTICS
VDDIO = 5V 5%, TA = 0C to 70C unless otherwise shown.
PARAMETER Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width High Video Input Data Setup Time Video Input Data Hold Time Video Output Data Delay Time Video Output Data Hold Time Address set up time Chip select set up time Read data access time Read data enable time Read data hold time Read pulse width Read cycle time Write data set up time Write data hold time Write pulse width Write cycle time Reset Pulse Width Device Latency
SYMBOL
CONDITIONS
MIN -
TYP 13 10
MAX 54 13 10 13 10
UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us PCLKs
tPWL tPWH tS tH tOD tOH tAS tACS tGQV tGQLZ tRDH tRD tRC tDS tWDH tWD tWC tRESET Multiplexer Mode Demultiplexer Mode with 10 pF loading with 10 pF loading
7.4 7.4 3 1 3 3 3 1 1 20 30 3 1 20 30 1 13 10
GS9023
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tH
DIN[9:0]
tS
PCLK
Fig. 14: Video Data Input Setup & Hold Times
GS9023
DOUT[9:0]
DATA VALID
tOH
PCLK
tOD
Fig. 15: Video Data Output Delay & Hold Times
Read Cycle
Write Cycle
tRC
ADDR[3:0]
tWC tAS
tAS
CS
tACS
RE
tRD tACS tWD tDS tWDH
WE
tGQV tGQLZ
tRDH
Valid Data
DATA[7:0]
Valid Data
Fig. 16: Host Interface Timing Diagram
VDDINT(min) VDDIO(min) VDDINT VDDIO
t RESET
t RESET
RESET
Fig. 17: Reset Timing Diagram
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Audio Channels (CH1/2/3/4) VIDEO IN
S/P DIN AINA AINB PCLK ACLK DEMUX/MUX WCIN DOUT
Audio Channels (CH5/6/7/8)
Audio Channels (CH9/10/11/12)
Audio Channels (CH13/14/15/16) VIDEO OUT
DIN AINA AINB PCLK
DOUT
DIN AINA AINB
DOUT
DIN AINA AINB
DOUT
P/S
ACLK DEMUX/MUX WCIN
CLK 54MHz 36MHz 27MHz 17.7MHz 14.3MHz
PCLK ACLK DEMUX/MUX WCIN
PCLK ACLK DEMUX/MUX WCIN
GS9023
PLL
CPU
Group DID No.
Fig. 18: Multiplex Mode Cascadable Architecture NOTE: In the 525/D1 video format, only 15 channels of 24 bit audio can be multiplexed
VIDEO INPUT WITH 16 CH. AUDIO DATA S/P CLK 54MHz 36MHz 27MHz 17.7MHz 14.3MHz 10 DIN DOUT 10 AUDIO OUTPUT CH. 1/2 AUDIO OUTPUT CH. 3/4 WORD CLOCK #1 WORD CLOCK #1
PLL
128fs(6.144MHz) Group DID No.
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023 #1
CPU 10 DIN DOUT 10 AUDIO OUTPUT CH. 5/6 AUDIO OUTPUT CH. 7/8 WORD CLOCK #2 WORD CLOCK #2
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023 #2 10 DIN DOUT 10
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023 #3 10 DIN DOUT 10
AUDIO OUTPUT CH. 9/10 AUDIO OUTPUT CH. 11/12 WORD CLOCK #3
WORD CLOCK #3
AOUTA AOUTB PCLK WCOUT VDD ACLK DEMUX/MUX GS9023 #4
AUDIO OUTPUT CH. 13/14 AUDIO OUTPUT CH. 15/16 WORD CLOCK #4
WORD CLOCK #4
Time
Fig. 19: Demultiplex Mode Parallel Architecture NOTE: The Group DID value set in the GS9023 via the Host Interface Port corresponds to the audio channels to be demultiplexed.
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PACKAGING INFORMATION
16.00 0.4 14.00 0.1 100 1 12 NOM View on A-A
GS9023
16.00 0.4 14.00 0.1 A A 12 NOM
+0.05 0.125 -0.025 0 MIN 10 MAX 0.50 0.2 1.0 REF
1.40 0.1
1.70 MAX
0.5
0.18 +0.1 -0.05
0.1
100 pin LQFP (FY) Dimensions in millimetres
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change.
REVISION NOTES: Clarified pin descriptions for pins 6-10, 12-16, 19-22, 54, 55, 70, and 91; Added a section called "Non-Standard Sample Distributions"; Added SMPTE compliance information to FEATURES; Added information to the FUNCTION column of CHACT(4-1) of Table15.
For latest product information, visit www.gennum.com
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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